Difference between revisions of "Quincy - Quartus Network Compiler"
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{{Project | {{Project | ||
|State=Completed | |State=Completed | ||
| − | |Members=Prodigity, | + | |Members=Prodigity, Danny Witberg |
|Description=Synthesizing FPGA designs on a VM! | |Description=Synthesizing FPGA designs on a VM! | ||
|Picture=Quincy_screenshot.png | |Picture=Quincy_screenshot.png | ||
Latest revision as of 15:50, 12 October 2016
| Project: Quincy - Quartus Network Compiler | |
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| Featured: | |
| State | Completed |
| Members | Prodigity, Danny Witberg |
| GitHub | No GitHub project defined. Add your project here. |
| Description | Synthesizing FPGA designs on a VM! |
| Picture | |
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tl;dr quincy/ or 192.168.1.131/
Compiling (or the more correct term: synthesizing) a FPGA design can take a very long time depending on the size and complexity of your creation.
Take in account that every person in the space that is doing stuff with FPGAs doesn't have the fastest hardware out there anymore something had to be done!
not really but any excuse counts tbh ;)
Meet Quincy, the solution to the problemthat barely existed!
Zip your fpga design, upload it to the server and it will compile your design for you!
It will show the current status and as soon as it's finished will allow you to download the sof and pof files.
As of now it seems to be running decently but undoubtedly bugs will probably pop-up,
please report them here:
