Clock jitter removal in VHDL

Project: Clock jitter removal in VHDL
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Members	Danny Witberg
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Description	Jitter removal in clock signals with VHDL implementation
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Unstable clock signals

Stable clock signals in digital domains is, generally speaking, something you should aim for, and desirable in most designs. A stable clock signal is reliable, and other circuits can depend on them. For instance, a reference signal to a PLL greatly depends on its stability in order for them to generate a higher frequency with a multiple oscillation frequency.

But what is this is not the case? What if your clock signal varies in frequency? This could really ruin your day! This project describes a way to stabilize a relative low frequency signal, with a much higher frequency, but stable, reference signal. To implement this inside an FPGA, an design is proposed in VHDL.

What is jitter?

A periodic variance in the frequency of a signal is called jitter. There can be a number of other unwanted characteristics to a clock signal, but jitter is one of the most common. The higher the jitter frequency, the more problems it could cause. Preferably, the jitter frequency would be 0Hz, but if you sample a clock with a higher frequency reference clock, you always end up with some sort of jitter. The VHDL implementation of this design converts a high jitter frequency to a lower one. Apart from the jitter frequency, also the amount that the jitter is influencing the signal should be reduced to a minimum. In short, the jitter frequency and amplitude must be reduced to increasethe clock quality.

The problem

So how is this jitter caused? For example, let's take a data link. This datalink is clocked at 25MHz, and is transmitting frames of information. The frequency of these frame is very important, and every 20.8uS, a full frame is transmitted. Because there is no common divider between the 25MHz datalink frequency and the 48kHz (20.8uS) frame repetition, a frame duration can be 521x bits in the datalink, or 520. Additional timing issues even can introduce frames of 519 or 521 bits. Because this 48kHz is fed into a PLL, the frequency must be as stable as can be.

The solution

A common divider between 25MHz and 48kHz is 150MHz. 150.000.000/25.000.000 = 6 and 150.000.000/48.000 = 3125. This is a very good choice of frequency if you want to exactly rate match the frame clock to the bit clock. However, if another frame clock is chosen, this is no longer valid and another solution has to be formed. A general master clock of 100MHz is chosen from a stable crystal oscillator. This means that, no matter what we try to do in VHDL, there will Always be some amount of jitter present in the frame clock. We can however try to minimize the effectiveness of the jitter, to keep its frequency and amplitude as low as possible.